1. Field of the Invention
The present invention generally relates to methods for forming a CMOS integrated circuit structure and to a semiconductor device structure, and, more particularly, to methods for forming a CMOS integrated circuit structure having a strained PMOS device and to strained semiconductor device structures.
2. Description of the Related Art
The majority of present-day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. Conventionally, present-day integrated circuits are implemented by millions of MOS transistors which are to be formed on a chip having a given surface area. An often-used technology for constructing present-day integrated circuits is provided by complementary metal oxide semiconductor (CMOS) technology. Current IC designs making use of CMOS technologies use complementary and symmetrical pairs of P-type metal oxide semiconductor field effect transistors, also called P-channel MOS transistors or PMOS transistors, and N-type metal oxide semiconductor field effect transistors, also called N-channel MOS transistors or NMOS transistors, for implementing logic functions and building varieties of logic structures.
The trend in IC fabrication is to incorporate more and more logic circuit structures on a single chip and to simultaneously improve the performance of the logic circuit structures. Consequently, a given area taken by logic circuitry on a chip has been steadily decreased, resulting in a scaling of the MOS structures and devices implementing logic circuit structures. However, scaling does not only enable improvement of chip performance, but also raises more and more challenges to cope with when scaling down MOS structures and devices to smaller dimensions.
One way of improving the performance of present-day circuits is achieved by techniques that apply mechanical stress to individual transistors to induce strained regions in the transistor. In particular, properly induced strain may be used to increase the mobility of majority carriers (holes for a PMOS transistor and electrons for an NMOS transistor) in the channel of a MOS transistor. One way to provide the proper strain is to form dual stress layers (DSL), sometimes also called “dual stress liners,” overlying the transistors. Tensile stress layers are formed over NMOS transistors and compressive stress layers are formed over PMOS transistors. The mobility of holes in the channel of PMOS transistors may be further increased by embedding silicon germanium at the ends of the channel to impart a compressive stress on the channel, while it is possible to further increase the mobility of electrons in the channel of NMOS transistors by embedding silicon carbide at the ends of the channel to impart a tensile stress on the channel.
In conventional CMOS fabrication techniques, silicon germanium stressor regions are embedded at the ends of the channel of a PMOS transistor after gate electrode formation. Subsequently, PMOS implants for forming halo regions and/or source and drain extension regions are performed, followed by NMOS implant steps for forming halo regions and/or source and drain extension regions.
An illustrative technique according to the prior art will be explained with regard to FIGS. 1a-1e. As illustrated in FIG. 1a, fabrication of a CMOS integrated circuit 100 begins by providing a semiconductor substrate 102, such as a silicon substrate. A PMOS region 104 is formed in one portion of semiconductor substrate 102 and an NMOS region 106 is formed in another portion. The two regions are separated by an electrical isolation structure, such as a shallow trench isolation (STI) 108. A gate electrode structure 110 of a PMOS transistor 111 overlies the PMOS region 104 and a gate electrode structure 112 of an NMOS transistor 113 overlies the NMOS region 106. The gate electrode structure 110 includes a gate insulator 114 and a conductive gate electrode 116. The gate electrode structure 112 includes a gate insulator 118 and a conductive gate electrode 120. Illustrative gate insulators are given by silicon dioxide, a high-k dielectric constant insulator or any other appropriate insulating material known to the person skilled in the art. The conductive gate electrodes 116 and 120 may be, for example, polycrystalline silicon or metal. The person skilled in the art appreciates that, depending on the exact process, a thin silicon-nitride (SiN) liner may be used to cover and protect a high-k/metal gate structure when performing gate-first integration.
As illustrated in FIG. 1b, the fabrication of CMOS IC 100 continues by forming sidewall spacers 122 on the sidewalls of the gate electrode structure 110. Conventionally, the sidewall spacers 122 may be silicon dioxide or silicon nitride and may be formed by blanket depositing a layer of sidewall spacer material 123 followed by an anisotropic etch process, such as reactive ion etching (RIE). During the etching of the sidewall spacers, the sidewall spacer material 123 overlying the NMOS region 106 is protected from the anisotropic etch by a photolithographically patterned etch mask 126, such as a patterned photoresist.
In accordance with the prior art fabrication technique, recesses 124 are subsequently etched into the PMOS region 104 using the gate electrode structure 110 and its associated sidewall spacer 122 as etch masks. The NMOS region 106 is protected during the recess etch process (not illustrated) by the photolithographically patterned etch mask 126 such that the recesses 124 are aligned to the gate electrode structure 110 of the PMOS transistor 111. As illustrated in FIG. 1b, recesses 124 border on the STI 108.
Following the etching of the recesses 124, the etch mask 126 is removed and the recesses 124 are filled with silicon germanium material to form embedded silicon germanium (eSiGe) 128 as illustrated in FIG. 1c. The eSiGe 128 may be grown by a process of selective epitaxial growth as is well known to those skilled in the art. The crystalline material bounding the recesses 124 acts as a nucleation site for the growth of single crystalline silicon germanium in the selective epitaxial growth process. If the conductive gate electrode 116 is of polycrystalline silicon, the polycrystalline silicon acts as a nucleation site for the deposition of polycrystalline silicon germanium 129. No silicon germanium grows on the insulating layers, such as the sidewall spacers 122, the remaining portion of the sidewall spacer material 123 overlying the NMOS region 106 and the STI 108, because of the growth process being selective. After the growth of eSiGe 128, the sidewall spacer 122 and the remaining portion of the sidewall spacer material 123 may be removed.
As illustrated in FIG. 1d, source and drain extension regions 132 are formed in alignment with the gate electrode structure 110 having sidewall spacers 134 formed at each side of the gate electrode structure 110. The source and drain extension regions 132 are formed by an ion implantation step 162 for implanting boron ions into the PMOS region 104 and into eSiGe 128. The NMOS transistor 113 is at the same time protected by a photolithographically formed resist mask 136 covering the gate electrode structure 112 and sidewall spacers 134 in the NMOS region 106 such that, in this processing phase, source and drain extension regions 132 are formed in the PMOS region 104.
Subsequent to the formation of source and drain extension regions 132 in the PMOS region 104, an according source and drain extension implant process 164 is applied to the NMOS transistors 113 as illustrated in FIG. 1e. While performing the source and drain extension implant step 164 in the NMOS region 106, the PMOS transistor 111 is protected and covered by a resist mask 146 which is formed over the PMOS region 104 by means of conventional photolithography techniques prior to performing the implantation step 164. As a result, source and drain extension regions 153 are formed in the NMOS region 106 in alignment with the gate electrode structure of NMOS 113.
The CMOS fabrication method as explained with regard to FIGS. 1a-1e exemplifies the CMOS fabrication for a single CMOS device. However, as noted above, conventional ICs are implemented by millions of MOS structures and devices which are designed in dependence of the application of the chip under fabrication. Depending on the design of the device under fabrication, the implemented IC may not only include one type of logic circuitry, such as SRAM, but may also include other logic devices, such as thick gate oxide devices for input/output applications and special devices with lower or higher threshold voltages, so-called low-Vth or high-Vth transistors, etc. In consequence, the actual number of implantations performed in typical CMOS fabrication flows may differ from 6-10 different implantation processes for source and drain extension implantations performed after formation of silicon germanium regions in typical CMOS fabrication flows. Each implantation requires a resist mask to protect the other devices during the implantation, the resist mask being removed after each implantation process by using a plasma strip process, for example, and subsequently applying a passivation cleaning process. Both processes, the strip process and the passivation cleaning process, inherently consume a small amount of the surface silicon in order to efficiently clean the substrate surface. However, this small amount of consumed surface adds up to a significant amount of active silicon loss which is even severe for silicon germanium since its etching rate is higher as compared to silicon.
FIG. 1f shows the PMOS device 111 after formation of sidewall spacer 184 and implantation of source and drain 192 into PMOS region 104. Spacer 184 corresponds to a spacer 1 structure used for aligning source and drain 192, while spacer 182 corresponds to a spacer 0 structure, used for implanting source and drain extension regions 132. The gate electrode structure 180 schematically represents a gate electrode stack according to gate-first techniques or a dummy gate electrode in accordance with gate-last or replacement gate techniques.
As illustrated in FIG. 1f, the amount of active silicon loss around the gate electrode structure 180 is represented by an arrow H representing a difference in surface level heights of the substrate surface at source and drain 192 (its extension being indicated in FIG. 1f by a broken line in order to allow visually relating both surface levels to each other) and the substrate surface above which the gate electrode structure 180 is disposed. The inventors observed that conventional fabrication steps as explained above amount to the active silicon loss H of around 8 nm resulting from the cleaning and passivation steps performed in between gate formation and spacer 1 formation during conventional CMOS fabrication flows.
As illustrated in FIG. 1f, the active silicon loss H around the gate electrode structure 180 of PMOS transistor 111 in PMOS region 104 results in a depression of the substrate surface around the gate electrode structure 180. Due to the depression of the substrate surface around the gate electrode structure 180, a warped current flow is expected to occur in the PMOS transistor 111 during operation, which is indicated in FIG. 1f by an arrow A. The person skilled in the art will understand that the depression of the substrate surface around the gate electrode structure 180 of PMOS transistor 111, therefore, contributes to an increased parasitic resistance of PMOS transistor 111. In general, depressions of substrate surfaces around gate electrodes of PMOS transistors as caused in conventional CMOS fabrication flows, therefore, reduce the on-current and switching speed of conventional PMOS transistors and, accordingly, of conventional CMOS structures and devices.
In view of the above discussion, there exists a need for methods of fabricating a CMOS integrated circuit structure and of semiconductor device structures providing CMOS structures with higher on-current and higher switching speed. Furthermore, there exists a need for PMOS integrated circuit structures with enhanced curing and switching characteristics as compared to conventional PMOS structures.
Particularly, there exists a need for methods of forming CMOS integrated circuit structures and a semiconductor device structure with enhanced performance and, in particular, for structures having a reduced amount of active silicon loss around the gate electrode, or even avoid any active silicon loss around the gate electrode.